1. Field of the Invention
This invention relates to programmable logic devices (PLDs), and more particularly to implementing multipliers in PLD RAM blocks.
2. Description of the Related Art
A PLD is a digital, user-configurable integrated circuit used to implement a custom logic function. For the purposes of this description, the term PLD encompasses any digital logic circuit configured by an end-user, and includes a programmable array logic array (“PLA”), a field programmable gate array (“FPGA”), and an erasable complex PLD. The basic building block of a PLD is a logic element (“LE”). A LE is capable of performing limited logic functions on a number of input variables. Conventional PLDs combine together multiple LEs through an array of programmable interconnects to facilitate implementation of both simple and complex logic functions.
U.S. Pat. Nos. 5,550,782 and 6,249,143 and commonly assigned U.S. patent application Ser. No. 10/140,311, filed May 6, 2002, entitled, Multiple Size Memories in a Programmable Logic Device, now U.S. Pat. No. 7,720,796 which are expressly incorporated herein by this reference, disclose the distribution of both relatively large random access memory (RAM) blocks and numerous smaller RAM blocks throughout a single programmable logic device. For example, U.S. Pat. No. 6,249,143 discloses smaller RAM blocks associated with groupings of LEs called logic array blocks (LABs). Each LAB includes an identical collection of multiple LEs, programmable interconnect wires and a RAM block dedicated to the LAB. Each LAB includes a two dimensional array of programmable interconnect wires that can be programmed to interconnect the LEs and RAM block of a given LAB. That patent also shows a two dimensional array of programmable global interconnect wires that can be programmed to interconnect the LEs and RAM blocks of different LABs and that also can be programmed to interconnect the larger RAM blocks with different LABs.
Digital signal processing encompasses arithmetic-intensive techniques used in applications such as voice-over-IP (Internet Protocol), wireless base station with multi-channel links, adaptive elements (i.e. equalizers) and echo cancellation, to name just a few illustrative examples. Many systems use digital signal processing techniques to achieve signal filtering to remove unwanted noise, to provide spectral shaping, or to perform signal detection or analysis, for example. Two types of filters that provide these functions are finite impulse response (FIR) filters and infinite impulse response (IIR) filters. The FIR filters generally are used in systems that require linear phase and have an inherently stable structure. The IIR filters are generally used in systems that can tolerate phase distortion. Typical filter applications include signal preconditioning, band selection and low-pass filtering. For instance, the finite impulse response (FIR) filter is used in many digital signal processing systems to perform signal pre-conditioning, anti-aliasing, band selection, decimation/interpolation, low-pass filtering, and video convolution functions.
Multipliers are one of the building blocks of any DSP application. In the past, PLDs have implemented multipliers using look-up tables. For instance, FIG. 1 is an illustrative schematic drawing showing one example of an interconnection of numerous PLD logic elements to implement a vector multiplier 20 used in a 7-bit input FIR filter. An eighth bit comes from adding two 7-bit taps. The vector multiplier 20 includes a shift register 22, multiple look-up tables (LUTs) 24. It also includes multiply and accumulate (MAC) circuitry that comprises an adder tree 25 including individual adders 26 and scaling multipliers 27.
One problem with the example multiplier implementation shown in FIG. 1 is that it consumes significant PLD resources in that numerous LUTs 24 are used to implement a multiplier. Some DSP applications require numerous multipliers. Unfortunately, the resources used by each individual multiplier can reduce the number of multipliers that can be implemented in any given PLD chip. Thus, there has been a need for improvements in the implementation of multiplier functionality in PLDs.
Another problem with prior multipliers implemented in a PLD is that they sometimes have been inconvenient to re-program, especially on-the-fly. For instance, in some adaptive filter applications, there is a need to adapt (or modify), filter coefficients while a filter is operational. Thus, there has been a need an improved PLD-based multiplier that can be re-programmed more easily on-the-fly, for adaptive filter applications, for example.
The present invention meets these needs.